A CISC (complex instruction set computer) type DSP (digital signal processor), which is a DSP with a highly complex instruction set, is equipped with a hardware resource that supports repeated structures in specific programs during DSP processing. It also has special instructions used for operating this hardware resource.
For example, when a filter operation or the like is carried out using a DSP, repeated processing is usually programmed. In order to carry out such a program efficiently, it is useful to adopt a special loop support mechanism for realizing the repetition without using a branch instruction.
When the loop support mechanism is used, the “repeated” operation (the operation of checking the number of repetitions and branching to the head of the loop if it is not finished) is automated. Ideally, the instructions during the loop can be executed without a cycle penalty.
The loop support mechanism is adopted in a DSP to express/retain the repetition structure during the program in a circuit at the address of the first/last instruction. It is also possible to use a special instruction for declaring a loop structure by initializing an address register that stores the address of the first/last instruction.
The address register of the loop support mechanism is initialized when the special instruction is executed by an instruction execution unit. The number of repetitions of the loop is indicated by initializing a number of repetitions register in advance using another instruction.
Then, the loop support mechanism interferes with instruction fetch so that repetition of the loop is performed without delay when the DSP is carrying out the loop. More specifically, the loop support mechanism indicates the loop head address where the instruction to fetch next is located when fetching reaches the loop end. Depending on this indication, the DSP can prepare the instruction to execute following the loop structure. In this way, the essential condition for repeating without any cycle penalty can be satisfied. Such a DSP can also have an instruction queue for the reason that instructions of variable length are used or the fetch width is not the instruction width.
Some DSPs developed in recent years also have a branch prediction mechanism used to reduce the number of cycles needed for executing control code in order to adapt to the case in which the proportion of DSP processing is reduced while the proportion of processing control code (a program or routine mainly composed of condition judgments and branching) is increased.
In the aforementioned CISC type of DSP, however, it is required to have both a loop support mechanism and a branch prediction mechanism in order to improve processing efficiency when the proportion of control code processing is increased.
However, since both the loop support mechanism and the branch prediction mechanism interfere with instruction fetch, if they are simply combined, optimal advanced instruction fetching may not be possible when these two mechanisms compete with each other. A complicated mechanism is needed to coordinate the two mechanisms to avoid this problem.
The objective of the present invention is to solve the aforementioned problem by providing a processor and a signal processing method that can process advanced fetching of a program in an optimal manner with a simple constitution when both a loop support mechanism and a branch prediction mechanism are present.